源码文件
package defcon is constant sreg_width :integer:=20; end defcon; use work.defcon.all; library ieee; use ieee.std_logic_1164.al…
DSP-CPLD 源代码
汇集 DSP-CPLD 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cDELED10 IS PORT( LIN:IN STD_LOGIC_VECTOR…
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity txmit is port( tx:out std_logic; --da…
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --use ieee.std_logi…
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in …
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity division1 is port( clk : in…
源码文件
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Speaker IS PORT ( clk1 : IN STD_LOGIC; Tone1 : IN INTEGE…
源码文件
library ieee; use ieee.std_logic_1164.all; entity decoder1 is port(cin:in std_logic_vector(7 downto 0); k1,k2:in std_lo…
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …