搜索：Cycles
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https://www.eeworm.com/dl/661/433575.html
FlashMX/Flex源码
Utils and test SD card read write cycles
Utils and test SD card read write cycles
https://www.eeworm.com/dl/644/147273.html
汇编语言
This package contains assembly programs for testing how many clock cycles a piece of code takes to
This package contains assembly programs for testing how many clock cycles
a piece of code takes to execute.
https://www.eeworm.com/dl/922661.html
技术资料
抗毁网状WDM网络中的光纤级P-Cycles优化设计
为降低保护切换代价和提高故障恢复时间，提出了以光纤级P-Cycle来实现网络保护；研究了工作路由与光纤级P-Cycle放置联合优化的设计问题，给出了ILP数学模型。为降低计算的复杂度，采用了一种
https://www.eeworm.com/dl/534/425107.html
其他
Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a pr
Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a program that reads in a vertex number and lists the number of edge disjoint cycles that start and end at this vertex. The output should also list the edges in each of the cycle disco ...
https://www.eeworm.com/dl/527/457359.html
通讯/手机编程
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read a
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested ...
https://www.eeworm.com/dl/918201.html
技术资料
Recording Total On-Time and Power Cycling Information Using the DS1682
The DS1682 provides a method of counting power cycles, total on-time, and alarm-on match functions
https://www.eeworm.com/dl/909354.html
技术资料
Recording Total On-Time and Power Cycling Information Using the DS1682
OVERVIEWThe DS1682 provides a method of counting power cycles, total on-time, and alarm-on match
https://www.eeworm.com/dl/532/336954.html
书籍源码
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK Description Toggle P5.1 u
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK
Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is
set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK.
Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles ar ...
https://www.eeworm.com/dl/534/480920.html
其他
Topics Practices: Programming and Numerical Methods Practice 1: Introduction to C Practice 2
Topics Practices:
Programming and Numerical Methods
Practice 1: Introduction to C
Practice 2: Cycles and functions
First part cycles
Part Two: Roles
Practice 3 - Floating point arithmetic
Practice 4 - Search for roots of functions
Practice 5 - Numerical Integration
Prac ...
https://www.eeworm.com/dl/648/257083.html
单片机开发
This example program shows how to configure PCA Module 4 as a watchdog timer. In this example, the
This example program shows how to configure PCA Module 4 as a
watchdog timer. In this example, the watchdog is configured to
overflow after 0xFF00 clock cycles.