实现产生伪随机序列的部件 —— 线性反馈移位寄存器单元。 SFlog2为扩频因子的底数为2的对数值，Cycle为PN序列的周期，其值为2^SFlog2。initial_state为移位寄存器的初始状态，generator_polynomial_coefficient为生成PN序列所需的本原多项式，对应于移位寄存器的连接向量。
上传时间： 2016-08-12
上传用户：zukfu
The purpose of this document is to present how to use the Timer for the generation of a PWM signal tunable in frequency and duty Cycle. As an application example, this document is based on a basic “music” synthesizer through an external buzzer. Example code is also available in the it.
标签： generation the document purpose
上传时间： 2013-12-20
上传用户：z754970244
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one Cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-13
上传用户：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one Cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-20
上传用户：三人用菜
完成在tigersharc201平台上划分出多个heap的操作，同时示例在多个heap之间切换时的方法，并做出各种内存下访问的Cycle统计
标签： tigersharc heap 201 分
上传时间： 2013-12-24
上传用户：坏天使kk
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction Cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.
标签： Microchip Routines Sample WRITE
上传时间： 2013-12-27
上传用户：ljmwh2000
It contains a vhdl description of the external bus interface unit for 68000 processor. currently only read and write Cycle are supported
标签： description currently interface processor
上传时间： 2017-03-16
上传用户：chenlong
Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a program that reads in a vertex number and lists the number of edge disjoint Cycles that start and end at this vertex. The output should also list the edges in each of the Cycle discovered. Input will be the adjacency matrix preceded by a 0 or 1 representing Directed or Undirected graphs respectively.
标签： undirected Disjoint directed Cycles
上传时间： 2017-04-08
上传用户：13188549192
蚁群算法经典TSP模型，ANT-Cycle算法的实现。 使用了C++的STL库。 原是我毕设的一部分 现在贡献出来 。 PS:网上能得到的基本上不能直接运行 而我这个复制到vc++6.0的控制台工程中即可 文件中的文件“oliver30Tsp.dat” 为实现蚁群算法的经典例子，网上还有很多类似的测试例子
上传时间： 2014-09-01
上传用户：Miyuki
This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo channels at a sampling frequency of 48 kHz. The Cycle register is embedded in the main program ( process_data.c) to benchmark the time needed to process two FIR fi lters. A background telemetry channel (BTC) is set up to display the Cycle count.
标签： experiment Blackfi EZ-KIT channe
上传时间： 2013-12-27
上传用户：baiom
