The UMTS Physical Layer model consists of an end-to-end (transmitter-to-receiver) simulation of the Frequency Division Duplex (FDD) Downlink physical layer for several Dedicated Channels (DCH) as specified by the 3GPP standard (Release 99).
标签： transmitter-to-receiver end-to-end simulation Physical
上传时间： 2014-01-10
上传用户：it男一枚
Algorithms for VLSI Physical Design Automation, 3E
标签： Algorithms Automation Physical Design VLSI for 3E
上传时间： 2018-03-14
上传用户：sjjoe
The Internet of Things is considered to be the next big opportunity, and challenge, for the Internet engineering community, users of technology, companies and society as a whole. It involves connecting embedded devices such as sensors, home appliances, weather stations and even toys to Internet Protocol (IP) based networks. The number of IP-enabled embedded devices is increasing rapidly, and although hard to estimate, will surely outnumber the number of personal computers (PCs) and servers in the future. With the advances made over the past decade in microcontroller,low-power radio, battery and microelectronic technology, the trend in the industry is for smart embedded devices (called smart objects) to become IP-enabled, and an integral part of the latest services on the Internet. These services are no longer cyber, just including data created by humans, but are to become very connected to the physical world around us by including sensor data, the monitoring and control of machines, and other kinds of physical context. We call this latest frontier of the Internet, consisting of wireless low-power embedded devices, the Wireless Embedded Internet. Applications that this new frontier of the Internet enable are critical to the sustainability, efficiency and safety of society and include home and building automation, healthcare, energy efficiency, smart grids and environmental monitoring to name just a few.
标签： Embedded Internet Wireless 6LoWPAN The
上传时间： 2020-05-25
上传用户：shancjb
The ever-increasing demand for private and sensitive data transmission over wireless net- works has made security a crucial concern in the current and future large-scale, dynamic, and heterogeneous wireless communication systems. To address this challenge, computer scientists and engineers have tried hard to continuously come up with improved crypto- graphic algorithms. But typically we do not need to wait too long to find an efficient way to crack these algorithms. With the rapid progress of computational devices, the current cryptographic methods are already becoming more unreliable. In recent years, wireless re- searchers have sought a new security paradigm termed physical layer security. Unlike the traditional cryptographic approach which ignores the effect of the wireless medium, physi- cal layer security exploits the important characteristics of wireless channel, such as fading, interference, and noise, for improving the communication security against eavesdropping attacks. This new security paradigm is expected to complement and significantly increase the overall communication security of future wireless networks.
标签： Communications Physical Security Wireless Layer in
上传时间： 2020-05-31
上传用户：shancjb
新一代FPGA综合技术,逻辑设计中出现的多个层次进行优化， 通过精简逻辑层次，提升了电路性能，并且降低了功耗
标签： Precision Physical 2010 2180
上传时间： 2013-06-12
上传用户：jlyaccounts
·Advanced ASIC Chip Synthesis Using Synopsys Design Compiler,Physical Compiler and Primetime
标签： nbsp Synthesis Advanced Synopsys
上传时间： 2013-04-24
上传用户：alia
Sensors for pressure, load, temperature, acceleration andmany other physical quantities often take the form of aWheatstone bridge. These sensors can be extremely linearand stable over time and temperature. However, mostthings in nature are only linear if you don’t bend them toomuch. In the case of a load cell, Hooke’s law states that thestrain in a material is proportional to the applied stress—as long as the stress is nowhere near the material’s yieldpoint (the “point of no return” where the material ispermanently deformed).
上传时间： 2013-11-12
上传用户：墙角有棵树
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
Abstract: Stuxnet, a sophisticated virus that damaged Iran's nuclear capability, should be an eye openerfor the world. We can choose to learn something very narrow (how to combat the Stuxnet virus) or wecan choose to focus on the larger goal of thwarting the next type of creative cyber attack. Unfortunately,critical industrial infrastructure is not currently designed with security as a key goal, leaving open multipleavenues for an educated and funded attacker to create massive problems. This tutorial outlines somebasic concepts that engineers and product definers should consider to make sure their new projects stayahead of future threats.
上传时间： 2013-11-17
上传用户：llwap
SDRAM的原理和时序 SDRAM内存模组与基本结构 我们平时看到的SDRAM都是以模组形式出现，为什么要做成这种形式呢？这首先要接触到两个概念：物理Bank与芯片位宽。1、 物理Bank 传统内存系统为了保证CPU的正常工作，必须一次传输完CPU在一个传输周期内所需要的数据。而CPU在一个传输周期能接受的数 据容量就是CPU数据总线的位宽，单位是bit（位）。当时控制内存与CPU之间数据交换的北桥芯片也因此将内存总线的数据位宽 等同于CPU数据总线的位宽，而这个位宽就称之为物理Bank（Physical Bank，下文简称P-Bank）的位宽。所以，那时的内存必须要组织成P-Bank来与CPU打交道。资格稍老的玩家应该还记 得Pentium刚上市时，需要两条72pin的SIMM才能启动，因为一条72pin -SIMM只能提供32bit的位宽，不能满足Pentium的64bit数据总线的需要。直到168pin-SDRAM DIMM上市后，才可以使用一条内存开机。不过要强调一点，P-Bank是SDRAM及以前传统内存家族的特有概念，RDRAM中将以通道（Channel）取代，而对 于像Intel E7500那样的并发式多通道DDR系统，传统的P-Bank概念也不适用。2、 芯片位宽 上文已经讲到SDRAM内存系统必须要组成一个P-Bank的位宽，才能使CPU正常工作，那么这个P-Bank位宽怎么得到呢 ？这就涉及到了内存芯片的结构。 每个内存芯片也有自己的位宽，即每个传输周期能提供的数据量。理论上，完全可以做出一个位宽为64bit的芯片来满足P-Ban k的需要，但这对技术的要求很高，在成本和实用性方面也都处于劣势。所以芯片的位宽一般都较小。台式机市场所用的SDRAM芯片 位宽最高也就是16bit，常见的则是8bit。这样，为了组成P-Bank所需的位宽，就需要多颗芯片并联工作。对于16bi t芯片，需要4颗（4×16bit=64bit）。对于8bit芯片，则就需要8颗了。以上就是芯片位宽、芯片数量与P-Bank的关系。P-Bank其实就是一组内存芯片的集合，这个集合的容量不限，但这个集合的 总位宽必须与CPU数据位宽相符。随着计算机应用的发展，
上传时间： 2013-11-04
上传用户：zhuimenghuadie
