并行计算的英文教程 Parallel Computation Architecture, Algorithm and Programming
标签： Architecture Computation Programming Algorithm
上传时间： 2016-12-31
上传用户：lo25643
Computation on GPUs: From A Programmable Pipeline to an Efficient Stream Processor
标签： Programmable Computation Efficient Processor
上传时间： 2017-01-18
上传用户：330402686
FRFT时频变换代码（参考算法：H.M. Ozaktas, M.A. Kutay, and G. Bozdagi.Digital Computation of the fractional Fourier transform.IEEE Trans. Sig. Proc., 44:2141--2150, 1996.）
标签： H.M. G. M.A. Computation
上传时间： 2013-12-21
上传用户：希酱大魔王
Shows how Linux futex syscall can be used to distribute Computation to multiple threads.
标签： Computation distribute multiple syscall
上传时间： 2017-02-20
上传用户：dave520l
This the Firmware code for the ADE7758 for the PIC Micro controller for the Computation of three phase parameters.
标签： the for Computation controller
上传时间： 2017-04-01
上传用户：lanwei
Mutual Information Computation
标签： Information Computation Mutual
上传时间： 2014-01-09
上传用户：z754970244
for parallel Computation
标签： Computation parallel for
上传时间： 2013-11-25
上传用户：cmc_68289287
在理论分析循环码编码和译码基本原理的基础上，提出了基于单片机系统的(24，16)循环码软件实现编码、译码的方案。仿真结果表明(24，16)循环码能有效地克服来自通讯信道的干扰，保证数据通信的可靠及系统的稳定，使误码率大幅度降低。本论文对(24，16)循环码的研究结果表明，可以有效地降低错误概率和提高系统的吞吐量，实现纠错仅需要在接收端增加有限的存储空间和计算复杂度，具有一定的实用价值。 Abstract: Based on analyzing the theory of encoding and decoding of cyclic code， this paper showed the schemes of encoding and decoding of(24，16)cyclic code by the software and based on microcontroller. Simulation results show that using (24，16) cyclic codes can effectively overcome the interference from communication channel， ensure the reliability and stability of data communication systems， and reduce the bit error rate greatly. The results of this paper show that by using the (24，16) cyclic code， the error rate can be reduced and the system throughput can be improved. Meanwhile， the system only needs to enlarge limited storage space and Computation the complexity at the receiving end to realize error correction. Thus the (24，16) cyclic code has a practical value.
上传时间： 2013-11-09
上传用户：gaoliangncepu
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andComputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上传时间： 2013-11-07
上传用户：swing
Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and Computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上传时间： 2013-10-12
上传用户：kang1923
