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其他 phase lock loop for coherent detection
phase lock loop for coherent detection
其他 This m file analyzes a coherent binary phase shift keyed(BPSK) and a amplitude shift keyed(ASK) comm
This m file analyzes a coherent binary phase shift keyed(BPSK) and a amplitude shift keyed(ASK) communication system. The receiver uses a correlator(mixer-integrator[LPF]) configuration with BER measurements comparing measured and theoretical results. The bandpass and low pass used in the receiver a ...
其他书籍 An Overview of the Coherent Acoustics Coding System(by Mike Smyth) 一本讲DTS编码细节的书,深入浅出
An Overview of the Coherent Acoustics Coding System(by Mike Smyth) 一本讲DTS编码细节的书,深入浅出
通讯/手机编程 Squaring circuits are an important building block for impulse-radio UWB non-coherent receivers. This
Squaring circuits are an important building block for impulse-radio UWB non-coherent receivers. This work proposes a squarer, based on the quadratic law of saturated transistors. Such a circuit has already been proposed for lower frequency applications, therefore this work focuses on the extension t ...
GPS编程 forming of a signal, GLONASS system, coherent reception, graph autocorrelation, crosscorrelation fun
forming of a signal, GLONASS system, coherent reception, graph autocorrelation, crosscorrelation function, bit-error probability[SNR]
matlab例程 Non coherent GPS signal acquistion file in MATLAB
Non coherent GPS signal acquistion file in MATLAB
邮电通讯系统 自己编的Coherent 8PSK
自己编的Coherent 8PSK，希望对大家有用，回头整理下再继续上传别的
教程资料 基于CPLD的QDPSK调制解调电路设计
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中 ...
可编程逻辑 基于CPLD的QDPSK调制解调电路设计
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中 ...
微处理器开发 The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and ...