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Active-HDL

Active-HDL是一款功能强大的硬件描述语言仿真工具，专为FPGA/CPLD设计验证而生。它支持VHDL、Verilog和SystemC等多种语言，提供直观的图形界面与高效的调试环境，极大提升了数字电路开发效率。无论是初学者还是资深工程师，都能通过丰富的示例项目快速掌握复杂系统的设计技巧。加入我...

资源总数

500

Active-HDL 热门资料

AAM原始Paper Active Appearance Models

AAM原始Paper Active Appearance Models

2016-07-03 23 Active-HDL

TI Handbook of OPA active RC networks

TI Handbook of OPA active RC networks

2014-11-16 36 Active-HDL

three_phase_three_wires_id_iq_method active filter deisgn in matlab&simulink

three_phase_three_wires_id_iq_method active filter deisgn in matlab&simulink

2017-07-23 133 Active-HDL

Active Filter Evaluation Board for Differential Amplifiers

The boards also have provisions for edge-mounted SMA connectors, which simplify testing and integ

2023-12-02 1 Active-HDL

HDL

Nice Book to learn Verilog

2025-05-03 9 Active-HDL

PURPLE: Predictive Active Queue Management Utilizing Congestion Information

PURPLE: Predictive Active Queue Management Utilizing Congestion Information

2015-12-16 78 Active-HDL

用VC开发Active的文档

用VC开发Active的文档，初学者的学习Active的不错的书

2013-12-30 95 Active-HDL

Microsoft Active Directory SDK 帮助文档

Microsoft Active Directory SDK 帮助文档

2014-10-13 105 Active-HDL

The Design of Active Crossovers by Douglas Self

各种常见分频器滤波器的设计，很详细，有计算参考

2023-02-23 10 Active-HDL

Verilog HDL程序 Verilog HDL程序

Verilog HDL程序 Verilog HDL程序

2017-01-29 20 Active-HDL