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A-MAX

  • MR-E-A伺服手册

    MR-E-A伺服手册

    标签: MR-E-A 伺服

    上传时间: 2013-10-30

    上传用户:半熟1994

  • 3d max 9.0中文版下载

        3dmax9.0 — 全世界最知名的3D动画制作软件 ,最新版本 3dmax9.0 已经于去年7月底在圣地牙哥正式发布了!3dmax9.0一直在动画市场上占有非常重要的地位,尤其在电影特效、游戏软件开发的领域里,discreet不断在改造出更具强大功能与相容性的软件来迎接这个新的视觉传播世代。 你可以在3dmax9.0最新版中,看到3dmax9.0如何帮助设计师与动画师更精准的掌握动画背景与人物结构,同时呈现出每个角色震撼的生命力.。 3dmax9.0 根据包括SEGA在内用户的要求,加强了游戏和电影特效的功能。 3dmax9.0 部分新功能如下:高级列表功能,查看和管理复杂场景。新软件包括了新的mental ray渲染器和可视工具。对Autodesk的CAD支持更好。分布式网络材质成型。创建现实的雾、雪、喷泉、弹着点等的质点流量系统。 3dmax9.0 新功能将包括: 高级浏览器,可以随时观看图片文件和max文件; 复杂的场景管理器用来管理大的场景; 整合的mental ray渲染器可以渲染出非常高质量的图片和动画、 顶点颜色绘制(vertex color painting); design visualization tools; 支持CAD、 动力学版本是reactor 2 ; distributed network texture baking; 3dmax9.0还增加了一些材质并整合了部分旧版本中常用的材质。除此之外,3dmax9.0为mental ray渲染器增添了多种材质。包括:DGS Material(physics_phen)、Glass(physics_phen)和mental ray 总的来说3dmax9.0的功能非常强大。

    标签: max 9.0 3d

    上传时间: 2013-11-17

    上传用户:zouxinwang

  • MR-E-A伺服手册

    MR-E-A伺服手册

    标签: MR-E-A 伺服

    上传时间: 2013-10-16

    上传用户:liaocs77

  • Create a 1-Wire Master with Xilinx PicoBlaze

    Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.

    标签: PicoBlaze Create Master Xilinx

    上传时间: 2013-11-12

    上传用户:大三三

  • AstroII-EVB-F1K(A)-L144开发板用户指南

        AstroII-EVB-F1K(A)-L144开发板用户指南

    标签: AstroII-EVB-F 144 开发板 用户

    上传时间: 2013-11-08

    上传用户:liuchee

  • CV181L-A-20_Specification_V1.0(大功放)

    cv181l-a-20

    标签: Specification_V 181 1.0 L-A

    上传时间: 2013-10-20

    上传用户:ikemada

  • Employing a Single-Chip Transceiver in Femtocell Base-Station Applications

    Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."

    标签: Base-Station Applications Single-Chip Transceiver

    上传时间: 2013-11-05

    上传用户:超凡大师

  • XAPP740利用AXI互联设计高性能视频系统

    This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

    标签: XAPP 740 AXI 互联

    上传时间: 2013-11-23

    上传用户:shen_dafa

  • powerPCB中的pcb转到protel中的pcb的方法

    如果用户现有的是 Protel99SE  。ProtelDXP,Protel2004 版本: 1 在powerpcb  软件的中打开 PCB 文件,选择导出 ASCII 文件(export  ascii  file) ,ascii  file 的版本应该选择 3.5 及以下的版本。 2  a 在 Protel99SE  。ProtelDXP  ,  选择 File->Import->在出现的对话框中,选择文件类型中的PADS Ascil Files (*.ASC)输入对应文件即可  1.powerpcb-->export ascii file--->import ascii file with protel99 se sp5(u must install padsimportor that is an add-on for 99sesp5 which can downloan from protel company ). 2.powerpcb-->export ascii file-->import ascii file in orcad layout-->import max file(orcad pcb file)with protel 99 or 99se.   

    标签: pcb powerPCB protel

    上传时间: 2013-10-16

    上传用户:whymatalab

  • 基于CPLD的QDPSK调制解调电路设计

    为了在CDMA系统中更好地应用QDPSK数字调制方式,在分析四相相对移相(QDPSK)信号调制解调原理的基础上,设计了一种QDPSK调制解调电路,它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上,进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中,测试结果表明,调制电路能正确选相,解调电路输出数据与QDPSK调制输入数据完全一致,达到了预期的设计要求。 Abstract:  In order to realize the better application of digital modulation mode QDPSK in the CDMA system, a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase,and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.

    标签: QDPSK CPLD 调制解调 电路设计

    上传时间: 2013-10-28

    上传用户:jyycc