代码搜索:xilinx ise 开发教程

找到约 10,000 项符合「xilinx ise 开发教程」的源代码

代码结果 10,000
www.eeworm.com/read/219731/14867470

prj time_tst_bencher.prj

verilog work "time60.v" verilog work "time24.v" verilog work "sec60.v" verilog work "time_go.v" verilog work D:/Software/Xilinx ISE8.2/verilog/src/glbl.v
www.eeworm.com/read/154076/5642967

sprj fdq.sprj

`timescale 1ns/1ns `include "fdq.vf" `include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
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sprj andnor2.sprj

`timescale 1ns/1ns `include "andnor2.vf" `include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
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sprj andnor2_p.sprj

`timescale 1ns/1ns `include "andnor2_p.vf" `include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
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sprj counter.sprj

`timescale 1ns/1ns `include "counter.v" `include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/428593/8857048

mf xilinx.mf

############################################################################### ## ## ## project-depen
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xilinx readme.xilinx

I've made a quick hack to support Xilinx HW-JTAG-PC cable. Connection is as follows: TCK --> SCK TDO --> MISO TDI --> MOSI TMS --> RESET# -- Tetsuya Okada Computer Creator
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run_xilinx

#!/bin/csh -f # setenv XVKMA_CORE_LUT_PACK TRUE setenv XIL_PAR_MAX_PLOAD 100 setenv XIL_GUIDE_CONNECTRPT 1 # ngdbuild -sd ../../src/xpci -sd ../synthesis \ -uc ../../src/ucf/v