代码搜索：wrapper
找到约 10,000 项符合「wrapper」的源代码
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www.eeworm.com/read/17583/740054
prj ps2_ports_io_adapter_wrapper_vhdl.prj
www.eeworm.com/read/17583/740289
prj plb_bram_if_cntlr_1_bram_wrapper_xst.prj
VERILOG plb_bram_if_cntlr_1_bram_elaborate_v1_00_a C:\myproj2\firewall\myxps\hdl\elaborate\plb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/verilog/plb_bram_if_cntlr_1_bram_elaborate.v
verilog work ../
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srp plb_bram_if_cntlr_1_bram_wrapper_xst.srp
Release 8.2.02i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL
www.eeworm.com/read/17583/740308
scr plb_bram_if_cntlr_1_bram_wrapper_xst.scr
run
-opt_mode speed
-opt_level 1
-p xc2vp30ff896-7
-top plb_bram_if_cntlr_1_bram_wrapper
-ifmt MIXED
-ifn plb_bram_if_cntlr_1_bram_wrapper_xst.prj
-ofn ../implementation/plb_bram_if_cntlr_1_bra
www.eeworm.com/read/17583/740323
scr ps2_ports_io_adapter_wrapper_xst.scr
run
-opt_mode speed
-opt_level 1
-p xc2vp30ff896-7
-top ps2_ports_io_adapter_wrapper
-ifmt MIXED
-ifn ps2_ports_io_adapter_wrapper_xst.prj
-ofn ../implementation/ps2_ports_io_adapter_wrapper.ng
www.eeworm.com/read/17583/740325
prj ps2_ports_io_adapter_wrapper_xst.prj
VERILOG dual_ps2_ioadapter_v1_00_a C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\dual_ps2_ioadapter_v1_00_a/hdl/verilog/dual_ps2_ioadapter.v
verilog work ../hdl/ps2_ports_io_adapter_w
www.eeworm.com/read/17583/740333
srp ps2_ports_io_adapter_wrapper_xst.srp
Release 8.2.02i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL
www.eeworm.com/read/39099/913832
srp system_processing_system7_0_wrapper_xst.srp
Release 14.2 - xst P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to D:\_prj\Xilinx\Blog\Lab4\synthesis\xst_temp_dir\
Total REAL time to Xst completi
www.eeworm.com/read/39099/913833
prj system_my_axi_ip_0_wrapper_xst.prj
vhdl proc_common_v3_00_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a/hdl/vhdl/family.vhd
vhdl proc_common_v3_00_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pc