代码搜索：when
找到约 10,000 项符合「when」的源代码
代码结果 10,000
www.eeworm.com/read/452795/7432672
vhd jh_cpu5.vhd
-- clock generation block
-- single/double byte(s) instruction fetch
-- single byte instruction expanded
-- jsr instruction expanded
-- bra instruction expand
library ieee ;
use ieee.std_logic_
www.eeworm.com/read/443322/7634618
bak spk.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity spk is
port(clk_6MHZ,CLK_4HZ:IN STD_LOGIC;
SPK:OUT STD_LOGIC);
END;
ARCHITECTURE ONE OF SPK IS
SIGNAL HML:S
www.eeworm.com/read/443322/7634685
vhd spk.vhd
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity spk is
port(clk_6MHZ,CLK_4HZ:IN STD_LOGIC;
SPK:OUT STD_LOGIC);
END;
ARCHITECTURE ONE OF SPK IS
SIGNAL HML:S
www.eeworm.com/read/135582/5884446
fl fast_slow.fl
# data file for the Fltk User Interface Designer (fluid)
version 1.00
header_name {.h}
code_name {.cxx}
gridx 10
gridy 10
snap 3
Function {} {open
} {
Fl_Window {} {open
xywh {143 188 318 4
www.eeworm.com/read/154890/5631672
fl fast_slow.fl
# data file for the Fltk User Interface Designer (fluid)
version 1.00
header_name {.h}
code_name {.cxx}
gridx 10
gridy 10
snap 3
Function {} {open
} {
Fl_Window {} {open
xywh {143 188 318 4
www.eeworm.com/read/135580/13920363
fl fast_slow.fl
# data file for the Fltk User Interface Designer (fluid)
version 1.00
header_name {.h}
code_name {.cxx}
gridx 10
gridy 10
snap 3
Function {} {open
} {
Fl_Window {} {open
xywh {143 188 318 4
www.eeworm.com/read/190618/8440643
c go.c
/*************************************************************
* File: mon/go.c
* Purpose: code for execution control
* Author: Phil Bunce (pjb@carmel.com)
* Revision History:
* 970216 Changed ty
www.eeworm.com/read/188207/8561025
vhd sao.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY sao IS
PORT(
clk : IN STD_LOGIC;
p8 : IN STD_LOGIC_VECTOR(3 downto 0);
p7 : IN STD_LOGIC_VECTOR(3 d
www.eeworm.com/read/419920/10829303
vhd sao.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY sao IS
PORT(
clk : IN STD_LOGIC;
p8 : IN STD_LOGIC_VECTOR(3 downto 0);
p7 : IN STD_LOGIC_VECTOR(3 d
www.eeworm.com/read/142489/12943233
vhd ch9_3_1.vhd
-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************