代码搜索：when
找到约 10,000 项符合「when」的源代码
代码结果 10,000
www.eeworm.com/read/370001/7154616
vhd imagexlib_utils.vhd
-- ************************************************************************
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- informa
www.eeworm.com/read/399935/7821176
vhd condsigm.vhd
-- MAX+plus II VHDL Example
-- Conditional Signal Assignment with Multiple Alternatives
-- Copyright (c) 1994 Altera Corporation
ENTITY condsigm IS
PORT
(
high, mid, low : IN BIT;
q
www.eeworm.com/read/198238/7946408
vhd 条件赋值：使用多路选择器.vhd
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/198238/7946524
txt 条件赋值：使用多路选择器.txt
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/197597/7984793
vhd 条件赋值：使用多路选择器.vhd
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/137517/13318020
vhd 条件赋值：使用多路选择器.vhd
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/323119/13351486
result case.result
drop table if exists t1;
select CASE "b" when "a" then 1 when "b" then 2 END;
CASE "b" when "a" then 1 when "b" then 2 END
2
select CASE "c" when "a" then 1 when "b" then 2 END;
CASE "c" when "a" then
www.eeworm.com/read/487908/6501834
vhd 条件赋值：使用多路选择器.vhd
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/263314/11367762
vhd condsigm.vhd
-- MAX+plus II VHDL Example
-- Conditional Signal Assignment with Multiple Alternatives
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm
www.eeworm.com/read/157209/11730138
txt 条件赋值：使用多路选择器.txt
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(