代码搜索：visual basic
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www.eeworm.com/read/269205/4247019
srr ram_basic.srr
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Wed Mar 08 21:20:06 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synp
www.eeworm.com/read/269205/4247020
srd ram_basic.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1
f "c:\prj\example-4-13\ram_basic\ram_basic.v"; #file 2
VNAME 'work.ram_basic.verilog'; # view id 0
@EuyRsFCDN88CRsbN0
www.eeworm.com/read/269205/4247021
srs ram_basic.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Wed M
www.eeworm.com/read/268663/4251049
h basic_prediction.h
#ifndef _BASIC_PREDICTION_H_
#define _BASIC_PREDICTION_H_
void CopyBlock(unsigned char * Src, unsigned char * Dst, int Stride);
void CopyBlockHor(unsigned char * Src, unsigned char * Dst, int
www.eeworm.com/read/268663/4251083
c basic_prediction.c
#include "basic_prediction.h"
void CopyBlock(unsigned char * Src, unsigned char * Dst, int Stride)
{
int dy;
#ifdef BIG_ENDIAN
char *lpSrc = (char *) Src;
char *lpDst = (char *) Dst
www.eeworm.com/read/449138/1680313
t 00_basic.t
BEGIN { $| = 1; print "1..1\n";}
END{ ok(!$loaded); }
require 't/config.pl';
$loaded = 0;
use SWF;
$loaded = 1;