代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
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www.eeworm.com/read/39713/1134937
100vhdl+
entity gcd is
port(start: in bit;
clk : in bit;
din : in bit;
xi,yi: in integer;
dout : out bit;
output:out integer);
end gcd;
architecture behavior of gcd is
begin
process
www.eeworm.com/read/39713/1134938
100vhdl+
www.eeworm.com/read/39713/1134939
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
entity gcd_tester is
end gcd_tester;
architecture test of gcd_tester is
signal start:bit :='0';
signal clk:bit :='0';
signal din:bit :='0';
signa
www.eeworm.com/read/39713/1134940
100vhdl+
-- Page : 278 - 278
--
-- Objective : wait until...
--
-- File Name : test_3.vhd
--
-- Author : Joseph Pick
--
entity Test_3 is
end Test_3;
architecture Behave_1 of Test_3 is
www.eeworm.com/read/39713/1134941
100vhdl+
www.eeworm.com/read/39713/1134942
100vhdl+
----------------------
PACKAGE bit_rtl_pkg is
----------------------
subtype short is integer range 0 to 65535;
subtype int4 is integer range 0 to 16;
subtype int8 is integer range 0
www.eeworm.com/read/39713/1134943
100vhdl+
use work.bit_rtl_pkg.all;
--------------------------------------
-- MUX2
-- 2 select 1 multiplexer
--------------------------------------
entity bit_rtl_mux2 is port (
in1 : in bit_vector;
www.eeworm.com/read/39713/1134944
100vhdl+
--**VHDL*************************************************************
--
-- SRC-MODULE : TESTBENCH
-- NAME : falsepath_stim.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Testbench for falsep
www.eeworm.com/read/39713/1134945
100vhdl+
www.eeworm.com/read/39713/1134946
100vhdl+
--**VHDL*************************************************************
--
-- SRC-MODULE : FALSEPATH
-- NAME : falsepath.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Architecture of FALSEPATH