代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
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www.eeworm.com/read/39713/1134917
100vhdl+
package logic is
type Bit_vector is array (Natural range ) of Bit;
end logic;
use WORK.logic.all;
entity And2 is
port( I1,I2: Bit; O1: out Bit);
end and2;
architecture And2_archit of
www.eeworm.com/read/39713/1134918
100vhdl+
www.eeworm.com/read/39713/1134919
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www.eeworm.com/read/39713/1134920
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entity bit_rtl_reg_clk is
port (
pin : bit_vector;
cntl : bit;
clk : bit;
pout : out bit_vector
);
end bit_rtl_reg_clk;
architecture func of bit_rtl_reg_clk is
begin
www.eeworm.com/read/39713/1134921
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www.eeworm.com/read/39713/1134922
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-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
www.eeworm.com/read/39713/1134923
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity tb_display_driver is
end tb_display_driver;
architecture tb of tb_display_driver is
component display_driver
www.eeworm.com/read/39713/1134924
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-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
www.eeworm.com/read/39713/1134925
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www.eeworm.com/read/39713/1134926
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--************VHDL********************
-- Module : 4-bit register
-- Name : register.vhd
-- Purpose: architecture of 4bit register
-- Comes from: XueYuan publication
-- Date: 1998,9,29
--****