代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
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www.eeworm.com/read/39713/1134907
100vhdl+
www.eeworm.com/read/39713/1134908
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_BAND is
-----------------------------------------------------------
generic(
www.eeworm.com/read/39713/1134909
100vhdl+
entity bit_rtl_lt_nc is
port (
in1 : bit_vector;
in2 : bit_vector;
pout : out bit
);
end bit_rtl_lt_nc;
architecture func of bit_rtl_lt_nc is
begin
process(in1,in2)
www.eeworm.com/read/39713/1134910
100vhdl+
www.eeworm.com/read/39713/1134911
100vhdl+
www.eeworm.com/read/39713/1134912
100vhdl+
--***************************************************************
-- Following first two examples show that object of std_logic and
-- object of logic can be assigned to each other
-- Bbut
www.eeworm.com/read/39713/1134913
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
package logic_pack is
function resolve(s : std_ulogic_vector) return std_ulogic;
SUBTYPE logic is resolve std_ulogic;
TYPE logic_vector IS ARRAY
www.eeworm.com/read/39713/1134914
100vhdl+
www.eeworm.com/read/39713/1134915
100vhdl+
package p is
attribute cycle_time:Time;
attribute max_cycles:Integer;
attribute clock_phases:Integer;
attribute Integer_width:Integer;
Type my_integer is range -2**15 to 2*
www.eeworm.com/read/39713/1134916
100vhdl+
--write by diao lan song
--1998/9/23
Use work.p.all;
ENTITY e_stim IS END e_stim ;
ARCHITECTURE stimulation OF e_stim IS
COMPONENT e_bus
port(bus1 : Inout wired_and my_intege