代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
代码结果 10,000
www.eeworm.com/read/39713/1134887
100vhdl+
package op_pkg is
subtype int3bit is integer range 0 to 7;
end op_pkg;
package synchro is
FUnction rising_edge(signal sig:bit) return boolean;
end synchro;
package body synchro is
www.eeworm.com/read/39713/1134888
100vhdl+
library work;
entity test_pid is
end test_pid;
architecture beh of test_pid is
component fu_pid
port
( reset : in bit;
Fsignin : in bit;
HostInterrupt : in bit;
Positi
www.eeworm.com/read/39713/1134889
100vhdl+
library work;
use work.synchro.all;
use work.op_pkg.all;
----------------------------------------------------------------
entity pid is
port (
reset : in bit;
Fsignin :
www.eeworm.com/read/39713/1134890
100vhdl+
-- Page : 346 - 348
--
-- Objective : dangers of the artificial usage of inout ports
--
-- File Name : test_195.vhd
--
-- Author : Joseph Pick
--
entity Component_Test_195 is
www.eeworm.com/read/39713/1134891
100vhdl+
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991 by Synopsys, Inc. A
www.eeworm.com/read/39713/1134892
100vhdl+
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.SIGNED_ARITH.all;
entity tb_e is
end tb_e;
architecture tb_a of tb_e is
signal clock,reset:std_logic;
si
www.eeworm.com/read/39713/1134893
100vhdl+
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.SIGNED_ARITH.all;
package coeffs is
type coef_arr is array (0 to 16) of signed (8 downto 0);
constant coef
www.eeworm.com/read/39713/1134894
100vhdl+
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.SIGNED_ARITH.all;
use work.coeffs.all;
entity fir is
port(clk,reset: in std_logic;
sample: in signed (
www.eeworm.com/read/39713/1134895
100vhdl+
www.eeworm.com/read/39713/1134896
100vhdl+
entity adder is
port (
in1 : in bit_vector;
in2 : in bit_vector;
pout : out bit_vector
);
end adder;
architecture func of adder is
begin
process(in1,in2)
begin