代码搜索:vhdl

找到约 10,000 项符合「vhdl」的源代码

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www.eeworm.com/read/32453/1034308

100vhdl+

entity mul is port ( in1 : bit_vector; in2 : bit_vector; cntl : bit; pout : out bit_vector ); end mul; architecture func of mul is begin process(cntl) begin
www.eeworm.com/read/32453/1034309

100vhdl+

entity delta is end entity; architecture archi_delta of delta is signal a : integer:=40; signal b : integer:=30; begin process begin a
www.eeworm.com/read/32453/1034310

100vhdl+

www.eeworm.com/read/32453/1034311

100vhdl+

--*************************************************************************** -- VHDL BIT_VECTOR Operations for MVL7 type --
www.eeworm.com/read/32453/1034312

100vhdl+

www.eeworm.com/read/32453/1034313

100vhdl+

function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
www.eeworm.com/read/32453/1034314

100vhdl+

www.eeworm.com/read/32453/1034315

100vhdl+

library IEEE; use IEEE.std_logic_1164.all; library dsp_lib; use dsp_lib.delay_macro.all; use dsp_lib.logic_pack.all; use dsp_lib.const_pack.all; ------------------------------------------ ent
www.eeworm.com/read/32453/1034316

100vhdl+

-- Page : 353 - 354 -- -- Objective : array signal multiplexing : error -- -- File Name : test_35b.vhd -- -- Author : Joseph Pick -- entity Test_35b is end Test_35b; archi
www.eeworm.com/read/32453/1034317

100vhdl+