代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
代码结果 10,000
www.eeworm.com/read/32453/1034228
100vhdl+
www.eeworm.com/read/32453/1034229
100vhdl+
----------------------
PACKAGE bit_rtl_pkg is
----------------------
subtype short is integer range 0 to 65535;
subtype int4 is integer range 0 to 16;
subtype int8 is integer range 0
www.eeworm.com/read/32453/1034230
100vhdl+
use work.bit_rtl_pkg.all;
--------------------------------------
-- MUX2
-- 2 select 1 multiplexer
--------------------------------------
entity bit_rtl_mux2 is port (
in1 : in bit_vector;
www.eeworm.com/read/32453/1034231
100vhdl+
--**VHDL*************************************************************
--
-- SRC-MODULE : TESTBENCH
-- NAME : falsepath_stim.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Testbench for falsep
www.eeworm.com/read/32453/1034232
100vhdl+
www.eeworm.com/read/32453/1034233
100vhdl+
--**VHDL*************************************************************
--
-- SRC-MODULE : FALSEPATH
-- NAME : falsepath.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Architecture of FALSEPATH
www.eeworm.com/read/32453/1034234
100vhdl+
www.eeworm.com/read/32453/1034235
100vhdl+
--------------------------------------------------------------------------------
--
-- Controller Counter Benchmark -- Simulation Vectors
--
-- Model Source: Chip Level modelling with VHDL by Ji
www.eeworm.com/read/32453/1034236
100vhdl+
--***************************************************************************
-- pack.vhdl *
-- VHDL BIT_VECTOR Ope
www.eeworm.com/read/32453/1034237
100vhdl+
--------------------------------------------------------------------------------
--
-- Controlled Counter Benchmark
--
-- Source: "Chip Level Modeling with VHDL" by Jim Armstrong (Prentice-Hall 19