代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
代码结果 10,000
www.eeworm.com/read/32453/1034168
100vhdl+
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
www.eeworm.com/read/32453/1034169
100vhdl+
www.eeworm.com/read/32453/1034170
100vhdl+
--------------------------------------------------------------------------------
--
-- FULL adder Benchmark -- Simulation Vectors
--
--
-- Authors :
-- Beijing Institute of Technolog
www.eeworm.com/read/32453/1034171
100vhdl+
--------------------------------------------------------------------------------
--
-- 4-Bit Full Adder
--
-- Benchmark author: Han Shu
--
-------------------------------------------------------
www.eeworm.com/read/32453/1034172
100vhdl+
--***************************************************************************
-- pack.vhdl *
-- VHDL BIT_VECTOR Ope
www.eeworm.com/read/32453/1034173
100vhdl+
www.eeworm.com/read/32453/1034174
100vhdl+
package op_pkg is
subtype int3bit is integer range 0 to 7;
end op_pkg;
package synchro is
FUnction rising_edge(signal sig:bit) return boolean;
end synchro;
package body synchro is
www.eeworm.com/read/32453/1034175
100vhdl+
library work;
entity test_pid is
end test_pid;
architecture beh of test_pid is
component fu_pid
port
( reset : in bit;
Fsignin : in bit;
HostInterrupt : in bit;
Positi
www.eeworm.com/read/32453/1034176
100vhdl+
library work;
use work.synchro.all;
use work.op_pkg.all;
----------------------------------------------------------------
entity pid is
port (
reset : in bit;
Fsignin :
www.eeworm.com/read/32453/1034177
100vhdl+
-- Page : 346 - 348
--
-- Objective : dangers of the artificial usage of inout ports
--
-- File Name : test_195.vhd
--
-- Author : Joseph Pick
--
entity Component_Test_195 is