代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
代码结果 10,000
www.eeworm.com/read/2252/14189
vhd vhdl.vhd
-- generated by newgenasym Wed Oct 22 09:35:55 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity sw2c is
port (
C: INOUT STD_LOGIC;
O: INOUT
www.eeworm.com/read/2252/14346
vhd vhdl.vhd
-- generated by newgenasym Tue Nov 04 09:42:25 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity ic_nand is
port (
IN1: IN STD_LOGIC;
IN2: IN
www.eeworm.com/read/2252/14439
vhd vhdl.vhd
-- generated by newgenasym Tue Nov 04 09:41:04 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity ic_inverter is
port (
\in\: IN STD_LOGIC;
\out\:
www.eeworm.com/read/2252/14454
vhd vhdl.vhd
-- generated by newgenasym Tue Nov 04 09:38:37 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity ic_and is
port (
IN1: IN STD_LOGIC;
IN2: IN
www.eeworm.com/read/2252/14642
vhd vhdl.vhd
-- generated by newgenasym Tue Dec 23 13:29:09 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity dsub25gnd is
port (
MT1: INOUT STD_LOGIC;
MT2: I
www.eeworm.com/read/2252/14659
vhd vhdl.vhd
-- generated by newgenasym Tue Dec 23 13:29:25 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity fci_10061913_102clf is
port (
A1: INOUT STD_LOGIC;
A1
www.eeworm.com/read/2252/14676
vhd vhdl.vhd
-- generated by newgenasym Tue Dec 23 13:28:53 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity smb is
port (
A: INOUT STD_LOGIC;
B0: INOUT
www.eeworm.com/read/2252/14695
vhd vhdl.vhd
-- generated by newgenasym Tue Oct 28 09:37:56 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity respoti is
port (
A: INOUT STD_LOGIC;
B: INO
www.eeworm.com/read/2252/14720
vhd vhdl.vhd
-- generated by newgenasym Wed Oct 29 14:21:42 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity res is
port (
A: INOUT STD_LOGIC;
B: INOUT
www.eeworm.com/read/2252/14741
vhd vhdl.vhd
-- generated by newgenasym Tue Nov 04 09:31:32 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity res4s is
generic (
size:positive:= 1
);
port (