代码搜索：vhdl

找到约 10,000 项符合「vhdl」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/2252/13679

vhd vhdl.vhd

-- generated by newgenasym Fri Oct 24 14:59:30 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity opampadj is port ( M: IN STD_LOGIC; N1: OU
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www.eeworm.com/read/2252/13696

vhd vhdl.vhd

-- generated by newgenasym Tue Oct 28 15:34:22 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity mt47j64m16 is port ( A0: IN STD_LOGIC; A1:
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www.eeworm.com/read/2252/13713

vhd vhdl.vhd

-- generated by newgenasym Thu Oct 23 15:04:42 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity ic574 is port ( C1: IN STD_LOGIC; D0: IN
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www.eeworm.com/read/2252/13730

vhd vhdl.vhd

-- generated by newgenasym Thu Oct 30 14:40:37 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity lt3080 is port ( \in\: IN STD_LOGIC; OUT1: OUT
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www.eeworm.com/read/2252/14071

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 29 11:37:46 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity dio is port ( A: INOUT STD_LOGIC; K: INOUT
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www.eeworm.com/read/2252/14096

vhd vhdl.vhd

-- generated by newgenasym Fri Oct 24 13:50:15 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity diozener is port ( A: INOUT STD_LOGIC; K: IN
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www.eeworm.com/read/2252/14118

vhd vhdl.vhd

-- generated by newgenasym Thu Oct 23 15:29:46 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity trpnp is port ( B: INOUT STD_LOGIC; C: INOUT
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www.eeworm.com/read/2252/14135

vhd vhdl.vhd

-- generated by newgenasym Thu Oct 23 15:22:00 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity trnpn is port ( B: INOUT STD_LOGIC; C: INOUT
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www.eeworm.com/read/2252/14152

vhd vhdl.vhd

-- generated by newgenasym Thu Oct 23 15:10:38 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity trnchan is port ( D: INOUT STD_LOGIC; G: INO
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www.eeworm.com/read/2252/14169

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 22 08:54:20 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity rec2p is port ( AC1: INOUT STD_LOGIC; AC2: INOUT
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