代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585927
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_11 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585929
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_20 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585930
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585931
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s2_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
www.eeworm.com/read/159314/5585937
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdi_24 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585939
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_38 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585940
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_ethernet_1 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_rep
www.eeworm.com/read/159314/5585941
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gnd is
generic(
cds_action : string := "ignore"
);
port(
g : out vl_logic
);
end gnd;
www.eeworm.com/read/159314/5585945
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_40 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585947
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s4_s36 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integ