代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585878
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_f_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
www.eeworm.com/read/159314/5585883
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_i is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5585893
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_ii is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
www.eeworm.com/read/159314/5585896
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_iv_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
www.eeworm.com/read/159314/5585897
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_iii is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5585901
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585908
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ild_1u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585920
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_12 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585921
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_iii_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585923
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s4_s18 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer