代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
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www.eeworm.com/read/159314/5585834
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585843
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_19 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585844
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_f_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
www.eeworm.com/read/159314/5585847
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_infiniband_2 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idl
www.eeworm.com/read/159314/5585850
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_ii_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
www.eeworm.com/read/159314/5585857
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufdn_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585858
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fd is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q : ou
www.eeworm.com/read/159314/5585868
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_f_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
www.eeworm.com/read/159314/5585870
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585875
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuftn is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i