代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585744
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity md1 is
generic(
cds_action : string := "ignore"
);
port(
o : in vl_logic
);
end md1;
www.eeworm.com/read/159314/5585750
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s2_s4 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
www.eeworm.com/read/159314/5585758
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_36 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585767
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1_s2 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
www.eeworm.com/read/159314/5585772
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585781
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_dv2_15 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585783
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_s_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585787
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildi_1m is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585789
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufcf is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585790
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_n_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo