代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585712
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufgdll is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585713
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildi_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585714
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufg_f is
port(
o : out vl_logic;
i : in vl_logic
);
end bufg_f;
www.eeworm.com/read/159314/5585722
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ld_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585729
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_13 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585730
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ild_1f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585731
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s2_s18 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
www.eeworm.com/read/159314/5585734
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585739
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585741
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuftds is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ob