代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585584
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufs is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585586
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585594
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_33 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585595
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_06 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585596
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufns_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5585606
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s2_s2 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
www.eeworm.com/read/159314/5585610
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufdn_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5585614
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufds is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ob
www.eeworm.com/read/159314/5585619
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_29 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585622
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_dv2_25 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in