代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585516
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
www.eeworm.com/read/159314/5585517
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s8_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
www.eeworm.com/read/159314/5585529
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
www.eeworm.com/read/159314/5585534
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
www.eeworm.com/read/159314/5585540
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildi_1f is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585546
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufds is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
io
www.eeworm.com/read/159314/5585548
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifd is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q : o
www.eeworm.com/read/159314/5585549
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_xaui_4 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_flag
www.eeworm.com/read/159314/5585560
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s1_s9 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
www.eeworm.com/read/159314/5585580
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufen_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e