代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585445
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufd_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585453
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_n_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5585455
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufds is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585464
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s2_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
www.eeworm.com/read/159314/5585477
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufn_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585502
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofd_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585506
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_s_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585507
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s4_s4 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
www.eeworm.com/read/159314/5585509
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585510
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_n_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic