代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585404
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdi is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5585407
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_f_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585417
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufg is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585425
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_dv2_33 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585426
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pulldown is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic
);
end pulldown;
www.eeworm.com/read/159314/5585432
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_05 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585435
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s4 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
www.eeworm.com/read/159314/5585440
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_28 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585441
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufsn is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585443
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufs_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i