代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585093
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufgp_f is
port(
o : out vl_logic;
i : in vl_logic
);
end bufgp_f;
www.eeworm.com/read/159314/5585095
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
www.eeworm.com/read/159314/5585097
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufgs is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585104
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_iv is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
www.eeworm.com/read/159314/5585107
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufdn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585108
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufdn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5585109
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_39 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585111
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_infiniband_1 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idl
www.eeworm.com/read/159314/5585119
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufd_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585129
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_42 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1