代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585052
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585053
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufs_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_log
www.eeworm.com/read/159314/5585055
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_dv2_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585056
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofd is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q : o
www.eeworm.com/read/159314/5585057
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_30 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585058
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufs_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_log
www.eeworm.com/read/159314/5585066
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_22 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585068
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity readback is
generic(
cds_action : string := "ignore"
);
port(
data : out vl_logic;
rip
www.eeworm.com/read/159314/5585077
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585080
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s8_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer