代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585007
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_24 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585010
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_10 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585013
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5585014
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585024
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_04 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585026
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ld is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q : ou
www.eeworm.com/read/159314/5585040
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_08 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585044
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ild_1m is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585045
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_n_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585046
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_gtlp_dci is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_