代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584897
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
www.eeworm.com/read/159314/5584920
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5584923
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_ethernet_2 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_rep
www.eeworm.com/read/159314/5584936
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584939
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufgp is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584940
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_ethernet_4 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_rep
www.eeworm.com/read/159314/5584941
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_16 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5584946
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity tdi is
generic(
cds_action : string := "ignore"
);
port(
i : inout vl_logic
);
end tdi;
www.eeworm.com/read/159314/5584954
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufsn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5584971
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_26 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1