代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584873
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_32 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5584874
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity buf is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584878
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufge is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584880
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufsn_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5584883
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s4_s9 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
www.eeworm.com/read/159314/5584889
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufd is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584891
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5584892
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity xorcy is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ci
www.eeworm.com/read/159314/5584894
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity buft is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584896
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufn is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i