代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584833
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_14 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5584835
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_aurora_1 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_fl
www.eeworm.com/read/159314/5584837
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5584839
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufsn_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584844
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdi is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5584850
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s4_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
www.eeworm.com/read/159314/5584855
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_01 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5584857
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufs_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5584858
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ild_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5584861
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_aurora_2 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_fl