代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/130423/14194867
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity keyscan is
generic(
sr : integer := 15;
s0 : integer := 14;
s1 : integer := 13;
www.eeworm.com/read/130423/14194892
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dff is
generic(
cardinality : integer := 1
);
port(
d : in vl_logic_vector;
q
www.eeworm.com/read/231687/14223281
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
www.eeworm.com/read/127647/14345900
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/127506/14351260
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/220307/14843468
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/220307/14843515
prj i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
www.eeworm.com/read/219736/14866536
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pa_se is
port(
clk : in vl_logic_vector(0 downto 0);
\in\ : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/219733/14866921
vif people4.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file peop
www.eeworm.com/read/219731/14867378
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity time_tst is
generic(
PERIOD : integer := 40;
DUTY_CYCLE : real := 0.500000;
OFFSET : integer :=