代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11692732
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
q : out
www.eeworm.com/read/347114/11692760
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo
www.eeworm.com/read/347114/11692787
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
q : out
www.eeworm.com/read/347114/11692855
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
www.eeworm.com/read/347114/11692939
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mo
www.eeworm.com/read/347114/11692956
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_
www.eeworm.com/read/347114/11693052
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
\MO\ : out vl_logic_vector(16 downto 0);
\A\ : in vl_logic_vector(16 downto 0);
www.eeworm.com/read/347114/11693349
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_8b10b_decoder is
port(
clk : in vl_logic;
reset : in vl_logic;
errdetectin : in
www.eeworm.com/read/347114/11693514
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity divide_by_two is
generic(
divide : string := "ON"
);
port(
clkin : in vl_logic;
clkout
www.eeworm.com/read/347114/11693570
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);