代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11690648
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
www.eeworm.com/read/347114/11690693
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo
www.eeworm.com/read/347114/11690699
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
q : out
www.eeworm.com/read/347114/11690766
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
\MO\ : out vl_logic_vector(16 downto 0);
\A\ : in vl_logic_vector(16 downto 0);
www.eeworm.com/read/347114/11690961
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altlvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_output: string
www.eeworm.com/read/347114/11690976
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altcam is
generic(
width : integer := 1;
widthad : integer := 1;
numwords : integer := 1;
www.eeworm.com/read/347114/11691061
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_8b10b_decoder is
port(
clk : in vl_logic;
reset : in vl_logic;
errdetectin : i
www.eeworm.com/read/347114/11691213
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity divide_by_two is
generic(
divide : string := "true"
);
port(
clkin : in vl_logic;
clkout
www.eeworm.com/read/347114/11691282
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(10 downto 0);
\A\ : in vl_logic_vector(10 downto 0);
www.eeworm.com/read/347114/11691482
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity apexii_jtagb is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo