代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/488254/6499666
hif sort4.hif
Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
7
2834
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Star
www.eeworm.com/read/488254/6499728
hif compare.hif
Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
7
2834
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Star
www.eeworm.com/read/488254/6499912
hif alu.hif
Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
7
2834
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Star
www.eeworm.com/read/488254/6500060
hif fdivision.hif
Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
7
2834
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Star
www.eeworm.com/read/487822/6500754
qmsg de2_lcm_ccd.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/486944/6521292
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/486944/6521335
prj i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
www.eeworm.com/read/482036/6635336
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/482036/6635342
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity front is
port(
clk_5m : in vl_logic;
rst : in vl_logic;
nd : in vl_logic;
www.eeworm.com/read/482036/6635357
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pingpang is
port(
clk_5m : in vl_logic;
rst : in vl_logic;
nd : in vl_logic;