代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/321790/13398866
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
clk : in
www.eeworm.com/read/321790/13398944
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
clk : in
www.eeworm.com/read/321790/13398962
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_tri is
port(
datain : in vl_logic;
dataout : out vl_logic;
oe : in vl_logi
www.eeworm.com/read/321790/13399043
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
mo : out vl_logic_vector(16 downto 0);
a : in vl_logic_vector(16 downto 0);
www.eeworm.com/read/321790/13399073
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mo
www.eeworm.com/read/321790/13399079
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altlvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_output: string
www.eeworm.com/read/321790/13399115
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altcam is
generic(
width : integer := 1;
widthad : integer := 1;
numwords : integer := 1;
www.eeworm.com/read/321790/13399193
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux41 is
port(
mo : out vl_logic;
in0 : in vl_logic;
in1 : in vl_logic;
www.eeworm.com/read/320782/13418405
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
www.eeworm.com/read/320782/13418470
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity textram is
port(
addr : in vl_logic_vector(12 downto 0);
clk : in vl_logic;
din