代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/298987/7901518
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/298987/7901751
qsf i2c_master_top.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/298987/7901789
prj i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
www.eeworm.com/read/398865/7913892
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/398865/7914066
prj i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
www.eeworm.com/read/433538/7923389
hif dk74x191.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
www.eeworm.com/read/297709/8002154
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity test_I2C_to_GPIO is
generic(
tdelay : real := 3.500000;
testcycle : real := 100.000000
);
end test_I2C_to
www.eeworm.com/read/297692/8004053
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode
www.eeworm.com/read/297692/8004107
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
mo : out vl_logic_vector(15 downto 0);
a : in vl_logic_vector(15 downto 0);
www.eeworm.com/read/297692/8004143
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo