代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5586023
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_sff is
port(
o : out vl_logic;
i : in vl_logic;
clk : in vl_logic;
www.eeworm.com/read/159314/5586028
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ram16 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i : i
www.eeworm.com/read/159314/5586040
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_srlc16e is
generic(
init : integer := 0
);
port(
q : out vl_logic;
q15 :
www.eeworm.com/read/159314/5586046
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_mux2 is
port(
o : out vl_logic;
ia : in vl_logic;
ib : in vl_logic;
www.eeworm.com/read/159314/5586055
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_rams128 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i :
www.eeworm.com/read/159314/5586056
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_tri is
port(
o : out vl_logic;
i : in vl_logic;
ctl : in vl_logic
www.eeworm.com/read/159314/5586059
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor2 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic
www.eeworm.com/read/159314/5586069
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor4 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;
www.eeworm.com/read/159314/5586072
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_suh is
port(
i : in vl_logic;
clk : in vl_logic;
ce : in vl_logic
www.eeworm.com/read/159314/5586284
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or3_fd is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer := 1
);