代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585798
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut3 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i0 : in
www.eeworm.com/read/159314/5585799
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fds_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5585806
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_pci66_3 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
www.eeworm.com/read/159314/5585808
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or5b1 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585810
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldce is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585812
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf5 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585816
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf8_d is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
lo
www.eeworm.com/read/159314/5585817
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5585819
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lde_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585821
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufn_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic;