代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585310
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_log
www.eeworm.com/read/159314/5585314
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_f_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585329
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_pcix66_3 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5585349
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fds is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q : o
www.eeworm.com/read/159314/5585351
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilffx is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585358
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_sstl2_i is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
www.eeworm.com/read/159314/5585367
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic;
www.eeworm.com/read/159314/5585369
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585372
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram32x4s is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
www.eeworm.com/read/159314/5585374
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x1d_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
dpo