代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585127
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflxi_1m is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585128
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdpe is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5585130
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585136
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_f_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585137
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdti_24 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
o
www.eeworm.com/read/159314/5585148
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_n is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic;
www.eeworm.com/read/159314/5585163
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram128x1s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585167
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_s_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585175
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_f_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585176
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom16x1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o