代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11691254
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and11 is
port(
\Y\ : out vl_logic_vector(10 downto 0);
\IN1\ : in vl_logic_vector(10 downto 0)
);
www.eeworm.com/read/347114/11691260
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
I9clNoF=RU4[`QRa?cQ?YI3
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/flex10ke_atoms.v)
L0 1144
OV;L
www.eeworm.com/read/347114/11691268
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dffe_io is
port(
\Q\ : out vl_logic;
\CLK\ : in vl_logic;
\ENA\ : in vl_logic;
www.eeworm.com/read/347114/11691442
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
IUIYT5QLzJmb`[BbkM]O>H2
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/apexii_atoms.v)
L0 238
OV;L;5.
www.eeworm.com/read/347114/11691449
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dffe_io is
port(
\Q\ : out vl_logic;
\CLK\ : in vl_logic;
\ENA\ : in vl_logic;
www.eeworm.com/read/347114/11691636
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
IS[7f_8GB^Gz4;2gI[a1O=3
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/mercury_atoms.v)
L0 176
OV;L;5
www.eeworm.com/read/347114/11691790
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/347114/11691934
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
I4n`W515:4NNF:J7K;ZWe61
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/apex20k_atoms.v)
L0 1575
OV;L;
www.eeworm.com/read/347114/11691940
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dffe_io is
port(
\Q\ : out vl_logic;
\CLK\ : in vl_logic;
\ENA\ : in vl_logic;
www.eeworm.com/read/347114/11692070
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);