代码搜索:verilog hdl 是什么?

找到约 10,000 项符合「verilog hdl 是什么?」的源代码

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mti ise_test.cr.mti

D:/Verilog/ise_test/params.v {1 {vlog -work work -novopt D:/Verilog/ise_test/params.v Model Technology ModelSim SE vlog 6.1f Compiler 2006.05 May 12 2006 } {} {}} D:/Verilog/ise_test/ddr_command.v
www.eeworm.com/read/204154/15343894

fld tiny16_maxii.fld

c:/otherquartusprojects/processor/verilog/tiny16/db/tiny16_MAXII.quartus_db tiny16_MAXII sgroom V1
www.eeworm.com/read/202736/15375130

rpt fcout.map.rpt

Analysis & Synthesis report for fcout Thu Apr 05 22:27:30 2007 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal N
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vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity and1 is port( y : out vl_logic; in1 : in vl_logic ); end and1;
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vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity stratix_asynch_lcell is generic( operation_mode : string := "normal"; sum_lutc_input : string := "datac"; lut_mask
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tcl ddr_cntl_a_xmdf.tcl

# The package naming convention is _xmdf package provide ddr_cntl_a_xmdf 1.0 # This includes some utilities that support common XMDF operations package require utilities_xmdf # Define a
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vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity ddr_sdram_tb is port( ); end ddr_sdram_tb;
www.eeworm.com/read/185226/9049482

gfl ledleft.gfl

# Compile HDL Simulation Libraries compxlib.log ledleft.cxl ledleft.compxlib_log # Compile HDL Simulation Libraries compxlib.log ledleft.cxl ledleft.compxlib_log # HDL Converter # XST (Creati
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mif rom0_factor_rom_i_1d1b3fe5.hdl.mif

-- begin_signature -- factor_rom_I -- end_signature WIDTH=16; DEPTH=64; ADDRESS_RADIX=UNS; DATA_RADIX=BIN; CONTENT BEGIN 63 : 0000000110010010; 62 : 0000001100100011; 61 : 00000100101
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mif rom0_cf_fft_1024_8_22_1ade68d6.hdl.mif

-- begin_signature -- cf_fft_1024_8_22 -- end_signature WIDTH=16; DEPTH=512; ADDRESS_RADIX=UNS; DATA_RADIX=BIN; CONTENT BEGIN 511 : 1000000011111111; 510 : 1000000011111110; 509 : 100