代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11692921
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and1 is
port(
\Y\ : out vl_logic;
\IN1\ : in vl_logic
);
end and1;
www.eeworm.com/read/347114/11693012
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_asynch_lcell is
generic(
operation_mode : string := "normal";
sum_lutc_input : string := "datac";
lut_mask
www.eeworm.com/read/347114/11693549
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_asynch_lcell is
generic(
operation_mode : string := "normal";
sum_lutc_input : string := "datac";
lut_mask
www.eeworm.com/read/347114/11693613
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and1 is
port(
\Y\ : out vl_logic;
\IN1\ : in vl_logic
);
end and1;
www.eeworm.com/read/347114/11693864
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity \NAND1\ is
generic(
\TPD\ : integer := 0
);
port(
\Y\ : out vl_logic;
\IN1\ : i
www.eeworm.com/read/347114/11694120
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity \FILTER\ is
port(
\Y\ : out vl_logic;
\IN1\ : in vl_logic
);
end \FILTER\;
www.eeworm.com/read/347114/11694224
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity \RISEFALL\ is
port(
\Y\ : out vl_logic;
\IN1\ : in vl_logic
);
end \RISEFALL\;
www.eeworm.com/read/347114/11694501
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity \NOR1\ is
generic(
\TPD\ : integer := 0
);
port(
\Y\ : out vl_logic;
\IN1\ : in
www.eeworm.com/read/347114/11694544
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity \DELAY\ is
generic(
\TPD\ : integer := 0
);
port(
\Y\ : out vl_logic;
\IN1\ : i
www.eeworm.com/read/347114/11694565
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity \INV\ is
generic(
\TPD\ : integer := 0
);
port(
\Y\ : out vl_logic;
\IN1\ : in